1. Field of the Invention
The present invention relates to a method of repairing a semiconductor memory by disconnecting a defective memory cell and connecting instead a redundancy memory cell in the semiconductor memory chip. The present invention is also concerned with an electron-beam memory repair apparatus and a redundancy memory circuit to which the method of repairing a semiconductor memory is applicable.
2. Description of the Prior Art
FIG. 1 of the accompanying drawings shows a semiconductor memory in a semiconductor memory chip on a semiconductor wafer, which includes a redundancy memory circuit comprising a redundancy cell. The semiconductor memory also includes normal memory cells 100 having 512 normal data lines with addresses 0xcx9c511, for example, and an address decoder 101 comprising logic gates 101a having respective output lines that are connected respectively to the 512 normal data lines through fuses 104a. Output addresses are selected by address lines {overscore (A0+L )}, A0, {overscore (A1+L )}, A1, . . . . The address line {overscore (A0+L )} represents an inversion of the address line A0.
The redundancy memory circuit includes a decoder 103 whose output is connected to a redundancy memory cell 102 through a redundancy data line. The address lines {overscore (A0+L )}, A0, {overscore (A1+L )}, A1, . . . are connected through respective fuses 104b to the inputs of the decoder 103. The redundancy memory circuit, which is made up of the redundancy memory cell 102, the redundancy data line, the decoder 103, and the fuses 104b, is normally in a disabled state. When an enable signal is applied, the disabled state of the redundancy memory circuit is canceled, and the output thereof is made effective.
The redundancy data line of the redundancy memory cell 102 in the redundancy memory circuit corresponds to the normal data lines of the normal memory cells 100. If the normal memory cell connected to the normal data line connected to the uppermost logic gate 101a, for example, is defective, then the fuse 104a connected to the output of the logic gate 101a is cut off, and fuses 104b connected to the input of the decoder 103 are cut off to use the redundancy data line connected to the redundancy memory cell 102 instead of the normal data line connected to the defective memory cell. In this manner, the normal data line connected to the defective memory cell is rendered ineffective, and the disabled state of the redundancy memory circuit is canceled by an enable signal, making effective the output of the redundancy memory cell 102 which is connected to the redundancy data line.
The fuses 104a, 104b are generally cut off by a laser-beam fuse cutting process. The principles of the laser-beam fuse cutting process will be described below with reference to FIGS. 2(a) through 2(d) of the accompanying drawings.
As shown in FIGS. 2(a) through 2(d), a semiconductor memory fuse region comprises an Si substrate 200, an insulating film 201 of SiO2 disposed on the Si substrate 200, a fuse layer 202 disposed on the insulating film 201 as an interconnection layer of aluminum, polysilicon, or the like, and an insulating film 204 of SiO2 disposed on the fuse layer. When a laser pulse shown in upper areas of FIGS. 2(a) through 2(d) is applied to the semiconductor memory fuse region, the energy of the applied laser pulse is absorbed by the fuse layer 202, whose temperature increases, as shown in FIG. 2(a). When the temperature of the fuse layer 202 rises, the energy absorption rate of the fuse layer 202 increases, resulting in an intensive pressure buildup in the fuse layer 202. The intensive pressure buildup in the fuse layer 202 causes the upper insulating film 201 of SiO2 to explode, allowing the fuse layer 202 to be vaporized, as shown in FIG. 2(b). When any remaining fuse layer is vaporized by the energy of a final portion of the laser pulse, the laser pulse reaches the lower insulating film of SiO2 (see FIG. 2(c)), which is slightly vaporized (see FIG. 2(d)). The fuse is cut off in the manner described above.
The laser-beam fuse cutting process is usually carried out by a mechanism which positions a laser beam quickly and highly accurately to a given fuse position in a semiconductor memory chip and applies the laser beam to cut off the fuse in the fuse position. The mechanism cuts off the fuse based on repairable wafer chip information and defective data line address information which have been obtained from a preliminary test conducted prior to the repairing process.
Recent highly integrated semiconductor memory chips are reduced in size by positioning fuses according to design rules which are employed so as to minimize the area which is occupied in the memory chip area by the fuses. There are strong demands for lowering the cost of the semiconductor memory chips. However, the conventional laser-beam fuse cutting process suffers the following shortcomings:
(1) The laser-beam fuse cutting process is required to selectively blow off only desired fuses in a manner to minimize damage to surrounding and lower silicon substrate regions. To meet such a requirement, it is necessary to use a laser beam having a wavelength which is equal to or longer than the infrared wavelength range. Because of the wavelength limitation, the laser beam spot diameter cannot be smaller than about 2.5 xcexcm.
(2) The positioning error of the mechanism for positioning a laser beam quickly and highly accurately to a given fuse position in a semiconductor memory chip is determined by the mechanical accuracy of the mechanism, and has a practical limit of about 0.3 xcexcm.
In view of the above two drawbacks of the conventional laser-beam fuse cutting process, it has been technically difficult to reduce the interval between fuses in a semiconductor memory chip to a distance of 2 (m or smaller. Therefore, efforts to minimize the area occupied by fuses in semiconductor memory chips have been subject to limitations.
In recent semiconductor memories, fuses are formed in the same layer as metal interconnections such as of aluminum or the like for the following reasons:
Semiconductor memories have a plurality of interconnection layers with metal interconnections in the uppermost layer and polysilicon interconnections in the lowermost layer. If the lowermost interconnection layer is used as a fuse layer, then it is necessary to etch back insulating and interconnection layers above the fuse layer in the vicinity of fuse regions. Due to variations in the thicknesses of the insulating and interconnection layers and also variations in the etchback process, it has been difficult to leave an insulating layer of stable thickness on the fuse layer in the environment of multiple interconnection layers. Consequently, fuses are generally formed in the uppermost layer.
The metal of the uppermost layer has a very high reflectance with respect to an infrared laser beam. Light that has entered the uppermost layer is absorbed by the surface thereof owing to the skin effect, and cannot reach a lower portion of the uppermost layer. For this reason, the power of the laser beam needs to be increased in order to cut off fuses in the uppermost layer. With the increased laser beam power, the layer underneath the uppermost layer tends to be damaged when fuses are cut off. It has thus been highly difficult to cut off minute fuses stably with a laser beam.
It is therefore an object of the present invention to provide a method of repairing a semiconductor memory by cutting off fuses which may be spaced at intervals of 2 xcexcm or smaller, without causing damage to a layer underneath the fuses.
Another object of the present invention is to provide an electron-beam memory repair apparatus and a redundancy memory circuit to which the above method of repairing a semiconductor memory is applicable.
According to a first aspect of the present invention, there is provided a method of repairing a semiconductor memory in a semiconductor memory chip by cutting off interconnections if a normal memory cell is defective, thereby to connect a redundancy memory cell in the semiconductor memory chip instead of the normal memory cell which is defective, comprising the steps of coating an entire surface of the semiconductor memory chip with a resist layer, exposing the resist layer at regions of the interconnections to an energy beam, developing the exposed resist layer to form a resist pattern, and etching the semiconductor memory chip at the regions using the resist pattern as a mask for thereby cutting off the interconnections.
According to a second aspect of the present invention, there is provided a method of repairing a semiconductor memory in a semiconductor memory chip by forming an interconnection if a normal memory cell is defective, thereby to connect a redundancy memory cell in the semiconductor memory chip instead of the normal memory cell which is defective, comprising the steps of coating an entire surface of the semiconductor memory chip with a resist layer, exposing the resist layer at a region where the interconnection is to be formed, to an energy beam, developing the exposed resist layer to form a resist pattern, etching the semiconductor memory chip at the region using the resist pattern as a mask, and depositing a deposition material in the region for thereby forming the interconnection.
According to a third aspect of the present invention, there is provided a method of repairing a semiconductor memory in a semiconductor memory chip by cutting off an interconnection and forming an interconnection if a normal memory cell is defective, thereby to connect a redundancy memory cell in the semiconductor memory chip instead of the normal memory cell which is defective, comprising the steps of coating an entire surface of the semiconductor memory chip with a resist layer, exposing the resist layer at a first region of the interconnection to an energy beam, developing the exposed resist layer to form a first resist pattern, etching the semiconductor memory chip at the first region using the first resist pattern as a mask for thereby cutting off the interconnection, exposing the resist layer at a second region where the interconnection is to be formed, to an energy beam, developing the exposed resist layer to form a second resist pattern, etching the semiconductor memory chip at the second region using the resist pattern as a mask, and depositing a deposition material in the second region for thereby forming the interconnection.
In each of the above methods, the energy beam may comprise an electron beam.
In the methods according to the second and third aspects, the redundancy memory cell may be connected-by an interconnection branched from a data line connected to the normal memory cell, the interconnection having a cut-off region, and the step of exposing the resist layer may comprise the step of exposing resist layer at the cut-off region to the energy beam, and the step of depositing a deposition material may comprise the step of depositing the deposition material in the cut-off region for thereby connecting the interconnection.
In the methods according to the second and third aspects, the deposition material may comprise polysilicon or a metal material.
According to the present invention, there is also provided an electron-beam memory repair apparatus to which either one of the above methods is applicable, comprising a memory tester for detecting a defective memory cell in a semiconductor memory chip on a semiconductor wafer, a repair image pattern generator connected to the memory tester, for generating a repair image pattern based on information with respect to the defective memory cell detected by the memory tester and information with respect to fuses and a redundancy memory cell, a stage for supporting the semiconductor wafer which has been coated with a resist layer on an entire surface thereof and moving the semiconductor wafer two-dimensionally, an electron-beam exposure system for applying an electron beam to the semiconductor wafer supported on the stage, and a controller for controlling the stage and the electron-beam exposure system based on the repair image pattern generated by the repair image pattern generator thereby to form an exposure pattern corresponding to the repair image pattern on the resist layer.
According to the present invention, there is further provided a redundancy memory cell to which the method according to the second or third aspect is applicable, comprising a redundancy memory cell disposed in a semiconductor memory chip and connected to an interconnection branched from a data line of a normal memory cell, the interconnection having a cut-off region.
In the methods described above, the semiconductor memory chip is selectively etched using the resist pattern as a mask to cut off or form an interconnection. Since the redundancy memory cell is connected by cutting off the interconnection, it is not necessary to use fuses of a conventional shape suitable for being cut off by a laser beam. Because the interconnection is cut off or formed by etching or deposition, substantially no damage is caused to a layer beneath the interconnection layer which is cut off or formed.
The area occupied by a region (fuse region) where the interconnection is cut off or formed is determined by the diameter of the energy beam used and the accuracy with which the semiconductor memory chip is positioned with respect to the energy beam. For example, if the energy beam comprises an electron beam, then the resist layer can be exposed at a resolution of submicrons or smaller, and a positional detection accuracy of 0.05 xcexcm or less can be achieved. Therefore, the area occupied by the region where the interconnection is cut off or formed is smaller than the area occupied by a fuse in the conventional process whose positional detection accuracy has suffered the practical limit of about 0.3 xcexcm. According to the present invention, the interval (fuse interval) between regions where the interconnection is cut off or formed can be reduced to 0.2 xcexcm.
In the redundancy memory circuit according to the present invention, the redundancy memory cell replaces the normal memory cell by connecting the cut-off region of the interconnection. The redundancy memory circuit does not need a decoder which has heretofore been required to replace the normal memory cell with the redundancy memory cell only by cutting off fuses.
With the methods according to the present invention, it is possible to cut off a fuse (interconnection) without damaging a layer underneath the fuse regardless of the material of the fuse (interconnection) to be cut off.
Inasmuch as it is not necessary to use fuses of a conventional shape suitable for being cut off by a laser beam, and the interval (fuse interval) between fuses can be reduced to 0.2 xcexcm, the area occupied by fuses (interconnections) to be cut off is smaller than the area occupied by fuses in the conventional process.
The electron-beam memory repair apparatus according to the present invention offers the above advantages while carrying out the above methods.
The redundancy memory circuit according to the present invention is relatively simple in structure and can be manufactured inexpensively as it does not need a decoder which has heretofore been required to replace the normal memory cell with the redundancy memory cell only by cutting off fuses.
The above and other objects, features, and advantages of the present invention will become apparent from the following description with references to the accompanying drawings which illustrate an example of the present invention.